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? semiconductor components industries, llc, 2015 november, 2015 ? rev. 0 1 publication order number: ncp81234/d ncp81234 dual-channel/two-phase controller for drmos the ncp81234, a dual?channel/two?phase synchronous buck controller, provides flexible power management solutions for applications supported by drmos. operating in high switching frequency up to 1.2 mhz allows employing small size inductor and capacitors. features ? single vin = 4.5 ~ 20 v with input feedforward ? integrated 5.35 v ldo ? vout = 0.6 v ~ 5.3 v ? fsw = 200 k ~ 1.2 mhz ? pwm output compatible to 3.3 v and 5 v drmos ? dual?channel or two?phase operation ? ddr power mode option ? interleaved operation ? differential current sense compatible for both inductor dcr sense and drmos iout ? 2 independent enables with programmable input uvlo ? programmable drmos power ready detection (drvon) ? 2 power good indicators ? comprehensive fault indicator ? externally programmable soft start and delay time ? programmable hiccup over current protection ? hiccup under voltage protection ? recoverable over voltage protection ? hiccup over temperature protection ? thermal shutdown protection ? qfn?28, 5x5 mm, 0.5 mm pitch package ? this is a pb?free device typical applications ? telecom applications ? server and storage system ? multiple rail systems ? ddr applications qfn28 mn suffix case 485bq device package shipping ? ordering information NCP81234MNTXG qfn28 (pb?free) 5000 / tape & reel marking diagram www. onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. xxxxxxxx xxxxxxxx awlyyww 1 xxxxx = specific device code a = assembly location wl = wafer lot yy = year ww = work week = pb?free package (note: microdot may be in either location) 28 1 vin 5 4 3 2 1 vcc5v en1 en2 pgood1 7 6 dly1 pgood2 gnd 29 isp1 17 18 19 20 21 isp2 isn1 pwm2 isn2 15 16 fb2 12 11 10 9 8 14 13 fset ss comp2 dly2 /ddr cnfg otp2 /refin ilmt2 24 23 22 28 27 26 25 ilmt1 pwm1 vref otp1 comp1 fb1 drvon fault pinout (top view)
ncp81234 www. onsemi.com 2 table 1. pin description pin name type description 1 vin power input power supply input. power supply input pin of the device, which is connected to the integrated 5 v ldo. 4.7 f or more ceramic capacitors must bypass this input to power ground. the capac- itors should be placed as close as possible to this pin. 2 en1 analog input enable 1. logic high enables channel 1 and logic low disables channel 1. input supply uvlo can be programmed at this pin for channel 1. 3 en2 analog input enable 2. logic high enables channel 2 and logic low disables channel 2. input supply uvlo can be programmed at this pin for channel 2. 4 drvon logic input driver on. logic high input means drivers? power is ready. 5 pgood1 logic output power good 1. open?drain output. provides a logic high valid power good output signal, indi- cating the regulator?s output is in regulation window of channel 1. 6 pgood2 logic output power good 2. open?drain output. provides a logic high valid power good output signal, indi- cating the regulator?s output is in regulation window of channel 2. 7 fault logic output fault. digital output to indicate fault mode. 8 dly1 analog input delay 1. a resistor from this pin to gnd programs delay time of soft start for channel 1. 9 dly2/ddr analog input delay 2 / ddr. a resistor from this pin to gnd programs delay time of soft start for channel 2. short to gnd to have ddr operation mode. 10 ss analog input soft start time. a resistor from this pin to ground programs soft start time for both channels. 11 fset analog input frequency selection. a resistor from this pin to ground programs switching frequency. 12 cnfg analog input configuration. a resistor from this pin to ground programs configuration of power stages. 13 ilimt2 analog input limit of current 2. voltage at this pin sets over?current threshold for channel 2. 14 otp2/refin analog input over temperature protection 2. voltage at this pin sets over?temperature threshold for channel 2. 15 comp2 analog output compensation 2. output pin of error amplifier of channel 2. 16 fb2 analog input feedback 2. an inverting input of internal error amplifier for channel 2. 17 pwm2 analog output pwm 2. pwm output of phase 2. 18 isn2 analog input current sense negative input 2. inverting input of differential current sense amplifier of phase 2. 19 isp2 analog input current sense positive input 2. non?inverting input of differential current sense amplifier of phase 2. 20 isn1 analog input current sense negative input 1. inverting input of differential current sense amplifier of phase 1. 21 isp1 analog input current sense positive input 1. non?inverting input of differential current sense amplifier of phase 1. 22 pwm1 analog output pwm 1. pwm output of phase 1. 23 fb1 analog input feedback 1. an inverting input of internal error amplifier for channel 1. 24 comp1 analog output compensation 1. output pin of error amplifier of channel 1. 25 otp1 analog input over temperature protection 1. voltage at this pin sets over?temperature threshold for channel 1. 26 ilimt1 analog input limit of current 1. voltage at this pin sets over?current threshold for channel 1. 27 vref analog output output of reference. output of 0.6 v reference. a 10 nf ceramic capacitor bypasses this input to gnd. this capacitor should be placed as close as possible to this pin. 28 vcc5v analog power voltage supply of controller. output of integrated 5.35 v ldo and power supply input pin of control circuits. a 4.7 f ceramic capacitor bypasses this input to gnd. this capacitor should be placed as close as possible to this pin. 29 therm/gnd analog ground thermal pad and analog ground. ground of internal control circuits. must be connected to the system ground.
ncp81234 www. onsemi.com 3 figure 1. typical application circuit for dual?channel applications ss vcc5v gnd vref en1 pgood1 pwm1 ncp81234 isn1 dly1 cnfg isp1 isp1 isn1 vin vout1 isp2 isn2 vin vout2 isp1 isn1 isn2 isp2 isp2 isn2 en1 pgood1 fset en2 pgood2 dly2 pgood2 vref fb2 comp2 vout2 fb1 comp1 vout1 vin en2 pwm vin vswh cgnd pgnd ncp5339 vcin disb# zcd_en# pwm2 pwm vin vswh cgnd pgnd ncp5339 vcin disb# zcd_en#
ncp81234 www. onsemi.com 4 figure 2. typical application circuit for two?phase applications ss vcc5v gnd vref en1 pgood1 ncp81234 isn1 dly1 cnfg isp1 isp1 isn1 vin vout1 isp2 isn2 vin isp1 isn1 isn2 isp2 isp2 isn2 en1 pgood1 fset vref fb1 comp1 vout1 vin en2 pwm1 pwm vin vswh cgnd pgnd ncp5339 vcin disb# zcd_en# pwm2 pwm vin vswh cgnd pgnd ncp5339 vcin disb# zcd_en#
ncp81234 www. onsemi.com 5 figure 3. typical two?phase application circuit for drmos with integrat ed current sense and temperature sense ss gnd en1 pgood1 pwm1 ncp81234 isn1 dly1 cnfg isp1 isp1 isn1 vin isp1 isn1 isn2 isp2 isp2 isn2 en1 pgood1 fset fb1 comp1 vout1 vin en2 vcc5v vref ilmt1 otp1 vtemp1 vout1 isp2 isn2 vtemp1 vin pwm2 pwm vin vswh cgnd pgnd ncp81293 iout tout refin pwm vin vswh cgnd pgnd ncp81293 iout tout refin vcc5v
ncp81234 www. onsemi.com 6 ilmt1 gnd pwm1 ncp81234 isp1 vin pwm2 dual?channel / two ?phase pwm control & protections isn1 cs1 isp2 isn2 cs2 current limit ilmt2 oc1 oc2 cs1 cs2 otp1 over temperature protection otp2/refin ot1 ot2 oc1 oc2 ot1 ot2 fb1 fb2 ss vcc5v vref pgood1 dly 1 fset 5v ldo reference programming detection cnfg dly 2/ddr uvlo & pgood pgood2 en2 en1 drvon fault fb1 comp1 fb2 comp2 0.6v mux refin comp1 comp2 figure 4. functional block diagram
ncp81234 www. onsemi.com 7 table 2. maximum ratings rating symbol value unit min max power supply voltage to pgnd v vin 30 v supply voltage vcc5v to gnd v vcc5v ?0.3 6.5 v other pins to gnd ?0.3 vcc5v + 0.3 v human body model (hbm) esd rating (note 1) esd hbm 2000 v machine model (mm) esd rating (note 1) esd mm 200 v latch up current: (note 2) all pins, except digital pins digital pins i lu ?100 ?10 100 10 ma operating junction temperature range (note 3) t j ?40 125 c operating ambient temperature range t a ?40 125 c storage temperature range t stg ?55 150 c thermal resistance junction to top case (note 4) r jc 5.0 c/w thermal resistance junction to board (note 4) r jb 3.8 c/w thermal resistance junction to ambient (note 4) r ja 38 c/w power dissipation (note 5) p d 2.63 w moisture sensitivity level (note 6) msl 1 ? stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. this device is esd sensitive. handling precautions are needed to avoid damage or performance degradation. 2. latch up current per jedec standard: jesd78 class ii. 3. the thermal shutdown set to 150 c (typical) avoids potential irreversible damage on the device due to power dissipation. 4. jedec standard jesd 51?7 (1s2p direct?attach method) with 0 lfm. it is for checking junction temperature using external measurement. 5. the maximum power dissipation (pd) is dependent on input voltage, maximum output current and external components selected. t a = 25 c, t j_max = 125 c, p d = (t j_max?t_amb )/theta ja 6. moisture sensitivity level (msl): 1 per ipc/jedec standard: j?std?020a.
ncp81234 www. onsemi.com 8 table 3. electrical characteristics (v in = 12 v, typical values are referenced to t a = 25 c, min and max values are referenced to t a from ?40 c to 125 c. unless other noted.) characteristics test conditions symbol min typ max unit supply voltage vin supply voltage range (note 7) v in 4.5 12 20 v vcc5v under?voltage (uvlo) threshold vcc5v falling v ccuv? 3.7 v vcc5v ok threshold vcc5v rising v ccok 4.3 v vcc5v uvlo hysteresis v cchys 260 mv vcc5v regulator output voltage 6 v < vin < 20 v, i vcc5v = 15 ma (external), en1 = en2 = low v cc 5.2 5.35 5.5 v load regulation i vcc5v = 5 ma to 25 ma (external), en1 = en2 = low ?2.0 0.2 2.0 % dropout voltage vin = 5 v, i vcc5v = 25 ma (external), en1 = en2 = low v do_vcc 200 mv supply current vin quiescent current en1 high, 1 channel and 1 phase only en1 and en2 high, 2 channel and 2 phase i qvin ? ? 15 18 20 25 ma vin shutdown current en1 and en2 low i sdvin ? 8 10 ma regulation reference regulated feedback voltage include offset of erro r amplifier 0 c to 85 c v fb 596 594 600 600 604 606 mv ?40 c to 125 c reference output vref output voltage i vref = 500 a v vref 594 600 606 mv load regulation i vref = 0 ma to 2 ma ?1.0 1.0 % voltage error amplifier open?loop dc gain (note 7) gain ea 80 db unity gain bandwidth (note 7) gbw ea 20 mhz slew rate (note 7) sr comp 20 v/ s comp voltage swing i comp(source) = 2 ma v maxcomp 3.2 3.4 ? v i comp(sink) = 2 ma v mincomp ? 1.05 1.15 fb, refin bias current v fb = v refin = 1.0 v i fb ?400 400 na differential current?sense amplifier dc gain gain ca 6 v/v ?3 db gain bandwidth (note 7) bw ca 10 mhz input common mode voltage range (note 7) ?0.2 v cc +0.1 v differential input voltage range (note 7) ?60 ? 60 mv input bias current isp,isn = 2.5 v i cs ?100 100 na product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 7. guaranteed by design, not tested in production.
ncp81234 www. onsemi.com 9 table 3. electrical characteristics (v in = 12 v, typical values are referenced to t a = 25 c, min and max values are referenced to t a from ?40 c to 125 c. unless other noted.) characteristics unit max typ min symbol test conditions switching frequency switching frequency rfs = 2.7k rfs = 5.1k float rfs = 8.2k short to gnd rfs = 13k rfs = 20k rfs = 33k f sw 180 270 360 450 540 720 900 1080 200 300 400 500 600 800 1000 1200 220 330 440 550 660 880 1100 1320 khz source current i fs 45 50 55 a system reset time system reset time measured from en to start of soft start with t dl = 0 ms t rst 1.8 2.0 2.2 ms delay time delay time float rdl = 33k rdl = 20k rdl = 13k rdl = 8.2k rdl = 5.1k rdl = 2.7k short to gnd (dly1 only) short to gnd (ddr mode, dly2 only) (note 7) t dl ? 0.9 1.8 2.7 3.6 7.2 10.8 18 ? 0 1.0 2.0 3.0 4.0 8.0 12 20 t dl1 ? 1.1 2.2 3.3 4.4 8.8 13.2 22 ? ms source current i dl 45 50 55 a soft start time soft start time otp configuration 1 (note 7) rss = 13k float rss = 20k rss = 33k t ss 0.9 2.7 3.6 5.4 1.0 3.0 4.0 6.0 1.1 3.3 4.4 6.6 ms otp configuration 2 (note 7) rss = 2.7k short to gnd rss = 5.1k rss = 8.2k 0.9 2.7 3.6 5.4 1.0 3.0 4.0 6.0 1.1 3.3 4.4 6.6 source current i ss 45 50 55 a configuration pwm configuration (note 7) channel 1 channel 2 cnfg pin is float pwm1 pwm2 cnfg shorted to gnd pwm1, pwm2 source current i cnfg 45 50 55 a pgood pgood startup delay measured from end of soft start to pgood assertion t d_pgood 100 s pgood shutdown delay measured from en to pgood de?assertion 240 ns pgood low voltage i pgood = 4 ma (sink) v lpgood ? ? 0.3 v pgood leakage current pgood = 5 v i lkgpgood ? ? 1.0 a fault fault output high voltage i source = 0.5 ma v fault_h v cc ?0.5 v product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 7. guaranteed by design, not tested in production.
ncp81234 www. onsemi.com 10 table 3. electrical characteristics (v in = 12 v, typical values are referenced to t a = 25 c, min and max values are referenced to t a from ?40 c to 125 c. unless other noted.) characteristics unit max typ min symbol test conditions fault fault output low voltage i sink = 0.5 ma v fault_l 0.5 v protections positive current limit threshold measured from ilimt to gnd isp?isn = 50 mv v octh+ 285 300 315 mv isp?isn = 20 mv 110 120 130 negative current limit threshold measured from ilimt to gnd (only active i n non?latched ovp) isp?isn = ?50 mv v octh? 285 300 315 mv isp?isn = ?20 mv 110 120 130 positive over current protection (ocp) debounce time (note 7) 8 cycles s under voltage protection (uvp) threshold voltage from fb to gnd v uvth 500 510 520 mv under voltage protection (uvp) hysteresis voltage from fb to gnd v uvhys 20 mv under voltage protection (uvp) debounce time (note 7) 1.5 s shutdown time in hiccup mode uvp (note 7) ocp (note 7) otp (note 7) 12*t ss 16*t ss 8*t ss ms first?level over voltage protection (ovp_l) threshold voltage from fb to gnd v ovth_l 650 660 670 mv first?level over voltage protection (ovp_l) hysteresis voltage from fb to gnd v lovhys ?20 mv first?level over voltage protection (ovp_l) debounce time (note 7) 1.0 s second?level over voltage protection (ovp_h) threshold voltage from fb to gnd v ovth_h 710 720 730 mv second?level over voltage protection (ovp_h) hysteresis voltage from fb to gnd v hovhys ?20 mv second?level over voltage protection (ovp_h) debounce time (note 7) 1.0 s offset voltage of otp comparator v ilmt = 200 mv v os_otp ?2 2 mv otp source current i otp 9 10 11 a otp debounce time (note 7) 160 ns thermal shutdown (tsd) threshold (note 7) t sd 140 165 c recovery temperature threshold (note 7) t rec 125 c thermal shutdown (tsd) debounce time (note 7) 120 ns enable en on threshold v en_th 0.75 0.8 0.85 v hysteresis source current vcc5v is ok i en_hys 25 30 35 a drvon drvon on threshold v drvon_th 0.75 0.8 0.85 v hysteresis source current vcc5v is ok i drvon_hys 25 30 35 a product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 7. guaranteed by design, not tested in production.
ncp81234 www. onsemi.com 11 table 3. electrical characteristics (v in = 12 v, typical values are referenced to t a = 25 c, min and max values are referenced to t a from ?40 c to 125 c. unless other noted.) characteristics unit max typ min symbol test conditions pwm modulation minimum on time (note 7) t on_min 50 ns minimum off time (note 7) t off_min 160 ns 0% duty cycle comp voltage when the pwm outputs remain lo (note 7) 1.3 v 100% duty cycle comp voltage when the pwm outputs remain hi, v in = 12.0 v (note 7) 2.5 v ramp feed?forward voltage range (note 7) 4.5 20 v pwm output pwm output high voltage i source = 0.5 ma v pwm_h v cc ?0.2 v pwm output low voltage i sink = 0.5 ma v pwm_l 0.2 v rise and fall times c l (pcb) = 50 pf, measured between 10% & 90% of v cc (note 7) 10 ns leakage current in hi?z stage i lk_pwm ?1.0 1.0 a product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 7. guaranteed by design, not tested in production. table 4. resistor options for function programming resistance range (k ) resistor options (k ) min typ max 5% 1% 2.565 2.7 2.835 2.7 2.61 2.67 2.74 2.80 4.845 5.1 5.355 5.1 4.87 4.99 5.11 5.23 7.79 8.2 8.61 8.2 7.87 8.06 8.25 8.45 12.35 13 13.65 13 12.4 12.7 13 13.3 19 20 21 20 19.1 19.6 20 20.5 31.35 33 34.65 33 31.6 32.4 33.2 34
ncp81234 www. onsemi.com 12 detailed description general the ncp81234, a dual?channel/two?phase synchronous buck controller, provides flexible power management solutions for applications supported by drmos. operating in high switching frequency up to 1.2 mhz allows employing small size inductor and capacitors. soft start the ncp81234 has a soft start function and the soft start time is externally programmed at ss pins. the output starts to ramp up following a system reset period t rst and a programmable delay time t dly after the device is enabled and both vcc5v and drvon are ready. the device is able to start up smoothly under an output pre?biased condition without discharging the output before ramping up. en vcc5v vout t rst t dly t ss pgood t d_pgood drvon pwm tri?state en vcc5v vout t rst t dly t ss pgood t d_pgood v ccok pwm tri?state drvon v drvon_ok (1) vcc5v and drvon ready before en (2) vcc5v and drvon ready after en figure 5. timing diagrams of power up sequence en vcc5v vout pgood drvon pwm tri ? state figure 6. timing diagram of power down sequence figure 7. timing diagram of drvon uvlo en vcc5v vout pgood drvon pwm t rst t dly t ss t d_pgood tri ? state v drvon _f v drvon _ok
ncp81234 www. onsemi.com 13 en en_int i en_hys v en_th vcc 5v vcc uvlo vcc ok drv on i drvon_hys v drvon_th figure 8. enable, drvon, and vcc uvlo enable and input uvlo the ncp81234 is enabled when the voltage at en pin is higher than an internal threshold v en_th = 0.8 v. a hysteresis can be programmed by an external resistor r en connected to en pin as shown in figure 9. the high threshold in enable signal is v en_h v en_th (eq. 1) the low threshold in enable signal is v en_l v en_th v en_hys (eq. 2) the programmable hysteresis in enable signal is v en_hys i en_hys r en (eq. 3) en en_int enable r en v en_th v en_h v en_l i en_hys figure 9. enable and hysteresis programming a uvlo function for input power supply can be implemented at en pins. as shown in figure 10 , the uvlo threshold can be programmed by two external resistors. v in_h r en1 r en2 1 v en_th (eq. 4) v in_l v in_h v in_hys (eq. 5) v in_hys i en_hys r en1 (eq. 6)
ncp81234 www. onsemi.com 14 en en_int vin r en1 r en2 v en_th v in_h v in_l i en_hys figure 10. enable and input supply uvlo circuit to avoid undefined operation, en pins cannot be left float in applications. ddr mode operation vddq otp2/ refin fb2 comp2 en1 en2 en dly2 / ddr 0.6v dac2 comp2 dly 2/ddr detector out high if pin is grounded. figure 11. block diagram of ddr mode operation vtt as shown in figure 11, if dly2/ddr pin is shorted to gnd before the device starts up, the ncp81234 is internally configured to operate in ddr mode. the two enable pins need to be connected together. the channel 1 provides power for vddq rail and the channel 2 provides power for vtt rail. the both channels have the same delay time programmed at dl y1 pin, and vtt rail always tracks with vddq/2. an external resistor divider, which is connected from vddq to gnd, is employed to get 0.6 v at refin pin in steady?state operation. another external resistor divider, which is connected from vtt to gnd, is applied to obtain an expected vtt voltage considering fb2 voltage is 0.6 v as refin. in ddr mode, two channels have independent fault detections and protections but have hiccup together if anyone of them needs to start a hiccup. over voltage protection (ovp) a two?level recoverable over voltage protection is employed in the ncp81234, which is based on voltage detection at fb pin. if fb voltage is over v ovth_l (660 mv typical) for more than 1 s, the first over voltage protection ovpl is triggered and pgood is pulled low. in the meanwhile, all the high?side mosfets are turned off and all the low?side mosfets are turned on. a negative current protection in low?side mosfets is active in this protection
ncp81234 www. onsemi.com 15 level, and it turns off low?side mosfet for at least 50 ns if negative current is over the limit. however, in a worse case that fb voltage rises to be over v ovth_h (720 mv typical) for more than 1 s, the second level over voltage protection ovph takes in charge. as same as the first level ovp, all the high?side mosfets are turned off and all the low?side mosfets are turned on, but the negative curren t protection is disabled. the over voltage protection can be cleared once fb voltage drops 20 mv lower than v ovth_l , and then the system comes back to normal operation. ovph detection starts from the beginning of soft?start time t ss and ends in shutdown and idle time of hiccup mode caused by other protections, while ovpl detection starts after pgood delay (t d_pgood ) is expired and ends at the same time as ovph. under voltage protection (uvp) the ncp81234 pulls pgood low and turns off both high?side and low?side mosfets once fb voltage drops below v uvth (540 mv typical) for more than 1.5 s. under voltage protection operates in a hiccup mode. a normal power up sequence happens after a hiccup interval. uvp detection starts when pgood delay (t d_pgood ) is expired right after a soft start, and ends in shut down and idle time of hiccup mode. over current protection (ocp) the ncp81234 senses phase currents by differential current sense amplifiers and provides a cycle?by?cycle over current protection for each phase. if ocp happens in all the phases of the same channel and lasts for more than 8 times of switching cycle, the channel shuts down and enters into a hiccup mode. the channel may enter into hiccup mode sooner due to the under voltage protection in a case if the output voltage drops down very fast. otp ilmt isp isn isp isn vref ocp otp r t3 r otp2 r otp1 r ntc 10ua r t1 r t2 6 otp ilmt isp isn isp isn vref ocp otp r ilim2 r otp2 r otp1 10ua r ilmt1 6 0.6v v t (1) otp configuration 1 (2) otp configuration 2 figure 12. over?current protection and over?temperature protection the over?current threshold can be externally programmed at the ilim pin for each channel. as shown in figure 12 (1), a ntc resistor r ntc can be employed for temperature compensated over current protection. the peak current limit per phase can be calculated by v isp v isn 1 6 r t3 r t1 r t2 r ntc r t2 r ntc r t3 v ref (eq. 7) if no temperature compensation is needed, as shown in figure 12 (2), the peak current limit per phase can be simply set by v isp v isn 1 6 r ilim2 r ilim1 r ilim2 v ref (eq. 8) ocp detection starts from the beginning of soft?start time t ss , and ends in shutdown and idle time of hiccup mode. over temperature protection (otp) the ncp81234 provides over temperature protection for each channel. to serve different types of drmos, one of two internal configurations of otp detection can be selected at ss pin combined with a soft start time programming. with otp configuration 1, as shown in figure 12 (1), the ntc resistor r ntc senses the hot?spot temperature and changes the voltage at ilmt pin. both over?temperature threshold and hysteresis are externally programmed at otp pin by a resistor divider. once the voltage at ilmt pin is higher than the voltage at otp pin, otp trips and the channel is shut down. the channel will have a normal start up after a hiccup interval in condition that the temperature drops below the otp reset threshold. the otp assertion threshold v otp and reset threshold v otp_rst can be calculated by
ncp81234 www. onsemi.com 16 v otp v ref i otp_hys r otp1 1 r otp1 r otp2 (eq. 9) v otp_rst v ref r otp2 r otp1 r otp2 (eq. 10) the corresponding otp temperature t otp and reset temperature t otp_rst can be calculated by t otp 1 ln r ntc_otp r ntc b 1 25 273.15 273.15 (eq. 11) t otp_rst 1 ln r ntc_otprst r ntc b 1 25 273.15 ?273.15 (eq. 12) where r ntc_otp 1 1 r t_otp r t1 1 r t2 (eq. 13) r ntc_otprst 1 1 r t_otprst r t1 1 r t2 (eq. 14) r t_otp v ref v otp 1 r t3 (eq. 15) r t_otprst v ref v otp_rst 1 r t3 (eq. 16) with otp configuration 2, as shown in figure 12 (2), the ncp81234 receives an external signal v t linearly representing temperature and compares to an internal 0.6 v reference voltage. if the voltage is over the threshold otp happens. the otp assertion threshold v otp and reset threshold v otp_rst in this configuration can be obtained by v t_otp 1 r otp1 r otp2 0.6 (eq. 17) v t_otp_rst 0.6 r otp2 i otp_hys r otp1 0.6 (eq. 18) otp detection starts from the beginning of soft?start time t ss , and ends in shutdown and idle time of hiccup mode. thermal shutdown (tsd) the ncp81234 has an internal thermal shutdown protection to protect the device from overheating in an extreme case that the die temperature exceeds 165 c. tsd detection is activated when vcc5v and at least one of ens are valid. once the thermal protection is triggered, the whole chip shuts down and all pwm signals are in high impedance. if the temperature drops below 125 c, the system automatically recovers and a normal power sequence follows. fault indicator the ncp81234 has a comprehensive fault indicator by means of a cycle?by?cycle fault signal output from fault pin. figure 13 shows a typical timing diagram of fault signal. fault signal is composed of aleart and two portions of fault flags for the two channels, having a total cycle period of 36 s. a corresponding fault flag is asserted to high once the fault happens. the periodic fault signal starts from the point where any fault has been confirmed and ends after pgood is asserted again. note the last fault cycle has to be complete after pgood assertion.
ncp81234 www. onsemi.com 17 pgood1 / pgood2 1 1 4 4 4 4 ov h ov l uv ot oc alert ov h ov l uv ot oc channel 1 fault flags channel 2 fault flags start interval end 2 36 fault figure 13. timing diagram of fault signal
ncp81234 www. onsemi.com 18 layout guidelines electrical layout considerations good electrical layout is a key to make sure proper operation, high efficiency, and noise reduction. electrical layout guidelines are: ? power paths: use wide and short traces for power paths (such as vin, vout, sw, and pgnd) in power stages to reduce parasitic inductance and high?frequency loop area. it is also good for efficiency improvement. ? power supply decoupling: the devices should be well decoupled by input capacitors and input loop area should be as small as possible to reduce parasitic inductance, input voltage spike, and noise emission. usually, a small low?esl mlcc is placed very close to vin and pgnd pins. ? vcc decoupling: place decoupling caps as close as possible to vcc5v pin of the ncp81234 and vccp pins of drmos. ? switching node: each sw node in power stages should be a copper pour, but compact because it is also a noise source. ? bootstrap: the bootstrap cap and an option resistor per phase need to be very close and directly connected between bootstrap pin and sw pin of drmos. ? ground: it would be good to have separated ground planes for power ground pgnd and analog ground gnd and connect the two planes at one point. ? voltage sense: use kelvin sense pair and arrange a ?quiet? path for the differential output voltage sense. careful layout for multi?phase locations and output capacitor distribution would help to get even voltage ripple at the voltage sensing point, and have better current balance as well. ? current sense: use kelvin sense pair and arrange a ?quiet? path for the differential current sense per phase. careful layout for current sensing is critical for jitter minimization, accurate current limiting, and good current balance. the current?sense filter capacitors and resistors should be close to the controller. the temperature compensating thermistor should be placed as close as possible to the inductor. the wiring path should be kept as short as possible but well away from the switch nodes. ? compensation network: the small feedback capacitor from comp to fb should be as close to the controller as possible. keep the fb traces short to minimize their capacitance to ground. thermal layout considerations good thermal layout helps high power dissipation from a small package with reduced temperature rise. thermal layout guidelines are: ? the exposed pads must be well soldered on the board. ? a four or more layers pcb board with solid ground planes is preferred for better heat dissipation. ? more free vias are welcome to be around drmos and underneath the exposed pads to connect the inner ground layers to reduce thermal impedance. ? use large area copper pour to help thermal conduction and radiation. ? do not put the inductor to be too close to the drmos, thus the heat sources are decentralized.
ncp81234 www. onsemi.com 19 package dimensions qfn28 5x5, 0.5p case 485bq?01 issue o seating note 4 k 0.15 c (a3) a a1 d2 b 1 8 15 28 e2 28x bottom view top view side view d a b e 0.15 c pin one indicator 0.10 c 0.08 c c 22 e a 0.10 b c 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.25mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. plane note 3 dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.20 0.30 d 5.00 bsc d2 3.15 3.35 e 5.00 bsc 3.35 e2 3.15 e 0.50 bsc l 0.45 0.65 l1 0.05 0.15 l1 detail a l alternate constructions l detail b detail a soldering footprint dimensions: millimeters 3.40 5.30 5.30 0.50 0.77 0.32 28x 28x pitch 1 3.40 recommended k 0.32 ref a m 0.10 b c a m 0.10 b c l m m ?? ?? detail b mold cmpd exposed cu alternate constructions ?? on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp81234/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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